1. Field of the Invention
The present invention relates to, inter alia, a reset signal generator for microcomputers and a hysteresis comparator for use in such a reset signal generator.
2. Description of the Related Art
The following description sets forth the inventor's knowledge of related art and problems therein and should not be construed as an admission of knowledge in the prior art.
In an electronics device equipped with a controller using a microcomputer, in order to prevent an abnormal power-on operation of the device, it is always necessary to activate the microcomputer at a constant state by supplying a reset signal for resetting the operation to the microcomputer. Conventionally, a comparator is used as a reset signal generating circuit in which a power supply voltage which rises from when the power supply is turned on and a predetermined reference voltage are compared, an “H” level signal is generated when the power supply voltage reaches the reference voltage or above.
In an electronics device, etc., using a battery as a power source, however, the power-on voltage may sometimes rise insufficiently and fluctuate. In such a case, if the power voltage to be applied to the comparator fluctuates around the reference voltage, an “H” level signal and an “L” level signal will be generated alternately, resulting in repetition of reset signals. Thus, the reset of the microcomputer would not be established. Conventionally, in order to prevent the aforementioned false reset operation, a comparator circuit having hysteresis characteristics with respect to the power supply voltage was used in a reset signal generation circuit.
FIG. 3 shows a circuit diagram showing a structure of a conventional comparator circuit having hysteresis characteristics. In FIG. 3, the reference numeral “1” denotes a series resistor portion consisting of a plurality of resistors 1a to 1f connected in series between the power supply voltage Vdd and the ground potential, the reference numeral “2” denotes a reference voltage supply for generating a reference voltage Vref, the reference numeral “3” denotes a comparator for comparing the voltage of the connecting midpoint of the resistors 1c and 1d and the reference voltage Vref, the reference numeral “4” denotes an inverter for inverting the output of the comparator 3, the reference numeral “5” is an inverter for inverting the output of the inverter 4, the reference numeral “6” denotes a switch MOS transistor which is turned on/off by the inverted output of the comparator 3, and the reference numeral “7” denotes an output terminal for outputting the output of the inverter 5 to the subsequent stage. In this example, it is assumed that the resistors 1a to 1f constituting the series resistor portion are equal in resistance with each other.
In the initial condition, if the power supply voltage Vdd is 0 V, the comparator 3 outputs an “L” level signal, which in turn makes the switch MOS transistor 6 turn off. In this state, since the switch MOS transistor 6 is turned off, the midpoint voltage of Vdd/2 is generated at the aforementioned connecting midpoint.
After the power source is turned on, the power supply voltage starts to rise. In accordance with the rising of the power supply voltage, the midpoint voltage at the connecting midpoint of the resistor 1c and the resistor 1d also rises. When the midpoint voltage becomes higher than the reference voltage Vref, the output of the comparator becomes an “H” level. The output of the comparator 3 is inverted by the inventors 4 and 5, and thus an “H” level reset signal will be outputted from the output terminal 7. On the other hand, the “L” level output of the inverter 4 is applied to the gate of the switch MOS transistor 6 to thereby turn on the switch MOS transistor 6. Since the ON resistance value of the turned-off state switch MOS transistor 6 is very small as compared with the values of the resistors 1a and 1b, it can be assumed that the power supply voltage Vdd is applied to the connecting midpoint of the resistor 1b and the resistor 1c. Thus, the power supply voltage Vdd will be divided by a total of four resistors 1c to 1f, and the voltage of the connecting midpoint of the resistors 1c and 1d becomes 3 Vdd/4.
As will be understood from the above, as the output of the comparator 3 changes from the “L” level to the “H” level, the midpoint voltage of the resistors 1c and 1d changes from Vdd/2 to 3 Vdd/4, or rises from Vdd/2 to 3 Vdd/4. In other words, the reference voltage Vref drops seemingly. As a result, even if the power voltage fluctuates after the generation of the reset signal, generation of false reset signals can be prevented (see, e.g., Japanese Unexamined Laid Open Patent Publication No. H05-48014).
In the meantime, in a conventional circuit as mentioned above, low power consumption of the reset signal generating circuit can be attained by increasing the resistance of the resistors 1a to 1f which exerts a large influence on the reset signal generating circuit. A conventional circuit generally employs a resistor such as a silicon resistor having resistance of about KΩ. In order to attain the low power consumption, however, it is required to employ a resistor having a resistance of about MΩ. On the other hand, the reset signal generating circuit is integrated together with a microcomputer. Generally speaking, such integration causes a larger resistance area of a resistor having large resistance. Accordingly, in a conventional circuit, it is necessary to increase the area of the poly silicon resistor to attain the low power consumption, which in turn causes an increased area of the IC chip.
In order to solve the aforementioned problems, it can be considered to employ a device such as a MOS transistor or a diffused resistor having a larger resistance per unit area as the resistors 1a to 1f. In such a case, however, the impedance of the MOS transistor or the diffused resistor as a resistor and that of the switch MOS transistor do not always coincide with each other to satisfy the specification of the reset signal generating circuit, and therefore the change in resistor voltage dividing due to the switching between the ON state and the OFF state of the switch MOS transistor 6 becomes small. Accordingly, after the generation of the reset signal, the midpoint voltage of the resistors 1c and 1d does not become high sufficiently. In other words, the reference voltage does not seemingly become low sufficiently. This may cause false reset signals due to the fluctuation of the power supply voltage.
The description herein of advantages and disadvantages of various features, embodiments, methods, and apparatus disclosed in other publications is in no way intended to limit the present invention. For example, certain features of the preferred embodiments of the invention may be capable of overcoming certain disadvantages and/or providing certain advantages, such as, e.g., disadvantages and/or advantages discussed herein, while retaining some or all of the features, embodiments, methods, and apparatus disclosed therein.